1. Technical Field
The present application relates generally to an improved data processing device and method. More specifically, the present application is directed to an apparatus and method for static random access memory (SRAM) array power reduction through majority evaluation.
2. Description of Related Art
Static random access memory (SRAM) is a type of semiconductor memory utilized in modern data processing devices. The term “static” indicates that SRAM is a memory type that retains its contents as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed. Nevertheless, SRAM should not be confused with read-only memory (ROM) and flash memory, since it is volatile memory and preserves data only while power is continuously applied. The term “random access” means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
In a typical architecture, each bit in an SRAM cell is stored on four transistors that form two cross-coupled inverters. This SRAM cell has two stable states which are used to denote 0 and 1 data values. Two additional access transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six metal-oxide-semiconductor field-effect transistors (MOSFETs) to store one memory bit.
FIG. 1 is an exemplary diagram of a known six transistor (6T) SRAM cell. Access to the SRAM cell 100 is enabled by the wordline (WL) 110 which controls the two access transistors 120 and 130. The two access transistors 120 and 130 control whether the memory cell 100 should be connected to bit lines BL 140 and BL′ 150. The bit lines BL 140 and BL′ 150 are used to transfer data for both read and write operations. The memory cell 100 further includes two inverters 160 and 170 which each comprise two transistors (not shown). The two transistors of each inverter 160 and 170 along with the access transistors 120 and 130 constitute the six transistors of the 6T SRAM cell structure. An SRAM memory array, comprising rows and columns of such SRAM cells 100, is typically used to provide a SRAM memory for a data processing device.
An SRAM cell 100 has three possible states: standby, read, and write. In a standby state, a signal along the wordline 110 is not asserted. As a result, the access transistors 120 and 130 disconnect the SRAM cell 100 from the bit lines BL 140 and BL′ 150. The two cross coupled inverters 160 and 170 continue to reinforce each other as long as they are disconnected from the bit lines BL 140 and BL′ 150.
In a read state, the bit lines BL 140 and BL′ 150 are precharged to a logical “1” or high voltage state. A signal along the wordline 110 is then asserted thereby enabling both of the access transistors 120 and 130. Assuming that the SRAM cell 100 stores a logic “1” value as Q, the values in the inverters 160 and 170, i.e. Q and Q′, are transferred to the bit lines BL 140 and BL′ 150 by leaving BL 140 at its precharged value and discharging BL′ 150, through the access transistor 130 and the NFET of inverter 160, to a logical “0” or low voltage state. On the BL 140 side, the voltage of bit line BL 140 is pulled towards VDD, i.e. a logical “1” or high voltage state, by the access transistor 130 and a PFET of inverter 170. If the content of the SRAM cell were a logic “0”, i.e. Q=0, the opposite situation would occur with the bitline BL′ 150 being pulled toward a logic “1” or high voltage state and bit line BL 140 being discharged towards a logic “0” or low voltage state.
The start of a write cycle begins by applying the value to be written to the bit lines BL 140 and BL′ 150. If a 0 value is to be written to the SRAM cell 100, a 0 value is applied to the bit lines, i.e. setting bitline BL′ 150 to a logic “1” or high voltage state and bitline BL 140 to a logic “0” or low voltage state. A 1 value may be written to the SRAM cell 100 by inverting the values of the bit lines BL 140 and BL′ 150. A signal along the wordline 110 is then asserted and the value that is to be stored is latched-in to the SRAM cell 100.
It should be noted that the reason this technique works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the SRAM cell 100 itself, so that they can easily override the previous state of the cross-coupled inverters 160 and 170. Careful sizing of the transistors in a SRAM cell 100 is needed to ensure proper operation.
Another known SRAM cell architecture makes use of eight transistors, i.e. an 8T SRAM cell, as shown in FIG. 2. In the eight transistor SRAM cell architecture, the write operation is performed in an identical manner as in the 6T SRAM cell described above with regard to FIG. 1. However, with this architecture, the bitlines BL 240 and BL′ 250 are not used for reading values from the SRAM cell 200.
To the contrary, in order to read from the 8T SRAM cell 200, a read bit line RBL 280 is provided and is precharged to a logic “1” or high voltage state. A read wordline 260 signal is then asserted causing the read port rp<n> to be enabled for all the SRAM cells 200 in a target row of the SRAM cell array. Based on the SRAM cell 200 contents, the read bit line RBL 280 is left in the precharge state, i.e. a logic “1” or high voltage state, or is discharged to a logic “0” or low voltage state. For example, if the content of the SRAM cell 200 is a “1” data value, then the read bit line RBL 280 is kept at a precharged state. If the content of the SRAM cell 200 is a “0” data value, the read bit line RBL 280 is discharged to a logic “0” or low voltage state. Depending on the speed at which the SRAM cell 200 can discharge the read bit line RBL 280, the read bit line RBL 280 holds the value of the target SRAM cell after the wordline signal is asserted and before the next precharge pulse clears the read bit line RBL 280.
The act of charging and discharging a bit line during a read operation consumes a large amount of energy in an SRAM array. Thus, it would be beneficial to reduce the amount of energy consumed by the SRAM array during accesses of the SRAM array.